keynote Speakers 2026

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keynote Speakers  CCE 2026

Prof. Marcelo Antonio Pavanello, PhD

Centro Universitario FEI, Sao Paulo, Brazil

Talk title: "Deep Cryogenic Operation of Planar and Tridimensional FD SOI MOSFETs for Quantum Computing"

Date: September 9, 2026

Hour: 10:30-11:30 (Mexico City central time zone, UTC-6)

https://fei.edu.br/~pavanello/

Participation of IEEE Student Branch Cinvestav-EDS

Plenary session sponsored by the DL program EDS

Short Biography:

Marcelo Antonio Pavanello (S´99-M´02-SM´05) received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998 he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor. Dr. Pavanello is Senior member of The IEEE and Brazilian Microelectronics Society. He is also Research Associate to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee of EDS in 2018. He is author and co-author of more than 300 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several Ph. D. dissertations, M. Sc. thesis and undergraduate projects in Electrical Engineering. His current interests are the compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.

Abstract:

The aggressive scaling of MOSFET dimensions triggered the search for alternative solutions for the traditional planar transistors for future technological nodes. Also, the advent of Quantum Computing raised interest in the cryogenic operation of ultimate MOSFETs for interface circuits between Qubits and electronic systems. Planar and tridimensional MOSFETs operating with fully depleted (FD) body fabricated in Silicon-On-Insulator (SOI) substrates are among the technological solutions being widely investigated.
Triple-gate Ω-shaped MOSFETs with fin height and width of similar dimensions, in the order of 10-15nm, commonly referred to as nanowires (NWs) in the literature, are promising contenders. One key challenge in scaling down transistors is achieving high drive current density per footprint while simultaneously preserving the excellent electrostatics of nanometer-scale MuGFETs, which is crucial for mitigating short-channel effects. To address these scaling limitations, vertically stacked nanosheet transistors have attracted
considerable attention. By layering multiple channels on top of each other, it allows for a significant increase in the current level per unit area, without sacrificing the electrostatic integrity inherently provided by nanometric MuGFETs. The experimental demonstration of seven-level stacked gate-all-around (GAA) nanosheet transistors achieved significant performance enhancements in both digital and analog applications, surpassing single-level transistors with similar structural characteristics. Moreover, due to their nanometer-
scale channels, quantum transport can be observed in aggressively scaled nanowires at cryogenic temperatures. In this scenario, this talk will present and discuss the operation of planar and tridimensional MOSFETs, both single-level and stacked with up to seven levels, when exposed to cryogenic temperatures down to 4 K. Peculiarities of these devices while operating in the cryogenic regime, such as transconductance oscillations indicating carrier confinement and self-heating, will be presented.

 

Prof. Romina Soledad Molina, PhD

KaleidoForge, Trieste, Italia

Talk title: "Neural Networks on FPGAs: The Path to Edge AI with KalEdge"

Date: September 10, 2026

Hour: 10:30-11:30 (Mexico City central time zone, UTC-6)

https://kaleidoforge.com/

Participation of IEEE Student Branch Cinvestav - Computer Society

Short Biography

Researcher and engineer specializing in Edge AI and embedded systems, with a PhD in Industrial and Information Engineering co-supervised by the University of Trieste, ICTP, and the National University of San Luis. Her work focuses on compressing and deploying machine learning models on FPGA and SoC platforms, with applications in nuclear instrumentation, precision agriculture, environmental monitoring, volcanology, and IoT. She is the founder of Kaleidoforge, an AI consultancy providing international training and development services, and actively collaborates with ICTP, IAEA, the University of Novi Sad, and the Ruđer Bošković Institute, among others.

Abstract:

Artificial intelligence no longer lives exclusively in the cloud. Increasingly, it needs to run directly on small, low-power devices such as sensors, instruments, and controllers close to where data is generated and acquired. This is the world of Edge AI, and FPGAs are emerging as an efficient option for achieving it, especially in applications requiring low latency, customized numerical precision, or resilience in demanding environments.
This talk shares real-world experiences deploying AI on FPGAs across very different fields, including radiation detection in nuclear instrumentation, crop monitoring in precision agriculture, and environmental monitoring. Behind these projects lies a common tool, hls4ml, which enables AI models to be translated into hardware-ready designs, making this technology accessible not only to hardware experts but also to researchers, engineers, and students from diverse backgrounds.
Building on lessons learned from both real-world deployments and educational activities, the talk examines recurring challenges encountered along the path from model design and compression to FPGA implementation. These challenges include fragmented toolchains, long design iterations, and the need for expertise spanning multiple domains. These experiences motivated the development of KalEdge, a hardware-aware platform that unifies dataset preparation, model design, compression-aware training, hardware-aware exploration, and FPGA deployment into a single end-to-end workflow based on hls4ml. The talk concludes with an overview of how KalEdge streamlines the machine-learning-to-bitstream process and helps lower the barrier to FPGA-based edge AI

Prof. Hugo Placido da Silva, PhD

University of Lisbon, Portugal

Talk title: "Invisibles: A New Frontier in Biomedical Signal Acquisition and Processing"

Date: September 11, 2026

Hour: 10:30-11:30 - (Mexico City central time zone, UTC-6)

https://www.embs.org/membership/chapters/distinguished-lecturers-program/distinguished-lecturers/hugo-silva/

Short Biography

Hugo Plácido da Silva is an award-winning inventor, researcher, and entrepreneur, having co-founded multiple innovative technology-based companies, operating in the fields of biomedical devices and data science for healthcare and quality of life. He obtained his Habilitation in Biomedical Engineering and completed his PhD in Electrical and Computers Engineering both from the Instituto Superior Técnico (IST), University of Lisbon (UL), where he is currently an Invited Assistant Professor. Hugo is also a Senior Researcher at the Instituto de Telecomunicações (IT), to which he is affiliated since 2004. Both at a technical and scientific level, he has actively contributed to more than 60 national and international projects, funded by grants from private and public institutions (e.g. Horizon Europe, Vodafone, or Nokia).

Hugo has 10 granted patents, co-authored 1 book, and published 260+ papers in peer reviewed journals, international refereed conferences, and as book chapters. His work has been distinguished both internationally and domestically with several awards, including the “IEEE Entrepreneurship Impact Award” and the “Career Award alumniIPS”, just to name a few. Hugo is an IEEE Member since 2010 (Senior Member since 2018), affiliated with the IEEE Engineering in Medicine and Biology Society. Furthermore, he is an active member of IEEE Region 8, where he is currently Industry Relations Coordinator of the IEEE Portugal Section and a Vice-Chair of the IEEE EMBS Portugal Chapter. More recently, he has also been appointed Member of the European Laboratory for Learning and Intelligent Systems (ELLIS) / Lisbon Unit for Learning and Intelligent Systems (LUMLIS).

Abstract:

An important part of clinical triage methods continues to be mostly bound to hospital and momentary data acquisition settings. Still, a paradigm shift is emerging, in which everyday technology is increasingly capable of measuring relevant biomedical signals in a more pervasive manner. This is paving the way for systems that can better analyze and adapt to perceived changes in the health status or behavior of the user. In this lecture we will characterize the current landscape of data acquisition and signal processing methods, describe state-of-the-art work developed towards what has been coined as the ”invisibles” approach, and provide a discussion of the main challenges posed by these new methodologies. Experimental results show that data acquired using such an approach is highly correlated with data obtained through conventional methods. This lecture will show real-world examples of devices integrated into everyday use objects with which users regularly interact with..